This invention relates generally to integrated circuits and more specifically to communications between two or more data processing circuits over a transmission line.
FIG. 1 shows a prior art part of a microprocessor system that would be a typical application for the invention. The system contains a microprocessor 1, connected to a numerical processor 3 by a plurality of bus lines 4. Microprocessor 1 includes a plurality of transceiver circuits 5 for transmission of signals on bus lines 4. Numerical processor 3 includes a plurality of transceiver circuits 6 also for transmission of signals on bus lines 4. Transceiver circuits 5 and 6 act as interfaces between the bus lines and the other circuitry of microprocessor 1 and numerical processor 3. A clock circuit 10 generates a system clock signal which is decoded on each chip into non-overlapping clock signals PHA and PHB that are used to clock all data transfers on bus lines 4. While FIG. 1 illustrates transceivers (5) built according to the invention communicating with other transceivers (6) built according to the invention, the invention is not limited to such applications. Transceivers built according to the present invention may be used to communicate with devices incorporating a variety of different bus interface circuitry, including asychronous devices not utilizing a shared system clock for data transfer.
In high performance microprocessors, a key factor limiting the overall speed of the system is the speed with which data signals can be sent over signal lines such as bus lines 4. The speed of data transmission over such lines in prior art systems have been generally limited by the electrical characteristics of the lines and of the driving circuits that drive the lines. In general, prior art systems have had to make a trade-off between transmission speed, power, and noise, i.e. the faster the prior art circuits attempted to transmit data on the lines, the more electrical noise was generated on the lines and on the power supplies of the driver circuit system.
In order to understand the nature of this trade-off, consider first FIG. 2A, which is a diagram of an idealized data signal on a bus line. This idealized representation of a digital data signal is a perfect "square wave" where the voltage on the line changes instantaneously from V.sub.ss (ground) to V.sub.dd when the information transmitted on the line changes from logical 0 to logical 1 and changes instantaneously from V.sub.dd to V.sub.ss when the information changes from 1 to 0. When a circuit wants to send a logical 0 (V.sub.ss) signal on the bus line, it must "pull down" the bus line to V.sub.ss and must "sink" sufficient current to pull down and hold the line at V.sub.ss for the duration of a data transfer cycle. When a circuit wants to send a logical 1 (V.sub.dd) signal on the bus line, it must "pull up" the bus line to V.sub.dd and must "source" sufficient current to pull up and hold the line at V.sub.dd for the duration of a data transfer cycle.
Now consider FIG. 2B, which illustrates a timing diagram of a typical real-world digital data signal on a bus line. In real-world circuits, it takes a finite amount of time for a bus driver circuit to move the voltage from V.sub.ss to V.sub.dd or vice versa. This amount of time is referred to as the rise time of the data signal, and the rate of change of the voltage on the line (dv/dt) is referred to as the slew rate. The duration of this rise time is determined by the driving characteristics of the electrical driver circuit putting data on the bus and by the electrical load (capacitance, inductance, and resistance) characteristics of the bus transmission line and of the circuit receiving the signal. FIG. 2B illustrates another respect in which a real-world digital bus signal varies from the idealized signal shown in FIG. 2A: bounce. Bounce is the result of the inductances inherent in real-world circuits and transmission lines. Bounce occurs on the transition from V.sub.dd to V.sub.ss and is characterized by the voltage on the bus line bouncing about V.sub.ss and then decaying exponentially to zero. Bounce also occurs on the transition from V.sub.ss to V.sub.dd where it is characterized by the voltage on the bus line bouncing about V.sub.dd and then decaying exponentially to V.sub.dd. Bounce creates high frequency noise on the bus line and in the power source and this noise can seriously degrade overall system performance. As indicated above, the amount of bounce is in part a function of the slew rate of the circuit in that the faster the slew rate, the more the signal on the line bounces.
FIG. 2B shows in detail the effects of slew time and bounce on the voltage level appearing on the transmission line. At a time t.sub.0, a driving circuit begins to put a logical 0 data signal on the bus line by lowering the voltage level to V.sub.ss. (Prior to time t.sub.0 the driving circuit is in an off or high-impedance state and the voltage on the line is at V.sub.dd.) Because it takes time for the driving circuit to sink current from the line in order to lower the voltage level, the voltage level does not reach V.sub.ss until a time t.sub.1. The interval t.sub.rt from time t.sub.0 to t.sub.1 is the rise time of the circuit and the slope of the voltage change during that rise time is the slew rate.
After time t.sub.1, the voltage on the line does not remain at V.sub.ss because of the interaction of the driving current and the inductance in the circuit. The voltage actually bounces about V.sub.ss and then decays towards V.sub.ss after time interval t.sub.b. After time t.sub.b, the voltage on the line becomes stable and the data may be read by a receiving circuit during time interval t.sub.v. At a time t.sub.3, the transmitting circuit begins to stop driving the data line. It takes the circuit a finite amount of time t.sub.off to completely stop driving the line and return to a high impedance state.
The duration of rise time t.sub.rt and the amount of bounce or ringing on the bus line generally act to limit the speed with which data may be transmitted on the bus line because the data cannot be read by the receiver until after the voltage on the bus line has risen or fallen to the proper level and has stabilized.
A third area of concern, in addition to bounce and slew rate, in high speed bus performance in real-world systems is bus contention. Bus contention occurs when two different bus users attempt to drive the bus to different logic levels at the same time. In a high speed bus, it is generally desired that new data be driven onto the bus as soon as the previous data is no longer being driven onto the bus. This means that at time t.sub.3 in FIG. 2B, a new bus transmitter would begin driving the bus line. Contentions arise because it takes the first transmitter a finite time t.sub.off to turn off its transmission. If the new transmitter begins driving the bus line to V.sub.dd while the previous transmitter is still driving the bus at or near V.sub.ss, a temporary short between V.sub.dd and V.sub.ss will result and can cause significant power drain and heat generation in the bus circuits.
Prior art bus driver circuits have reduced bounce generally by limiting the overall rate at which the circuits sink or source current on the bus line. While this strategy can effectively reduce bounce, it also slows down the data transmission rate on the bus because it increases the rise time of the bus. The increased transition time means that bus receivers must wait longer before latching data from the bus. Some prior art circuits have also attempted to reduce bounce by using feedback control from the external bus line to vary the rate at which current is sunk or sourced on the bus. This method has not worked well in some high speed microprocessor environments because the signal distortion and noise on the external bus line is so great that the feedback control cannot effectively control the rate of current sink or source on the bus.
It is therefore desired to fashion a bus driver circuit that minimizes bounce, without slowing down overall data transmission rates, and reduces bus contention.